RGMII, Reduced Gigabit Media-Independent Interface, is an interface standard between a FPGA and an Ethernet PHY supporting gigabit Ethernet. RGMII is an alternative to GMII with a reduced number of signals.

RGMII is clocking data on both rising and falling clock edges, double data rate, DDR.

Default FPGA Cores support 100 and 1000 Mbps full duplex. 10 Mbps can be added to the core upon request.

RGMII Signals

Signal nameDescriptionDirection
TXCClock signalFPGA to PHY
TXD[3..0]Data to be transmittedFPGA to PHY
TX_CTLMultiplexing of transmitter enable and transmitter errorFPGA to PHY
RXCReceived clock signalPHY to FPGA
RXD[3..0]Received dataPHY to FPGA
RX_CTLMultiplexing of data received is valid and receiver errorPHY to FPGA
MDCManagement interface clockFPGA to PHY
MDIOManagement interface I/OBidirectional

Cores Supporting RGMII


RGMII Implementation Details

By default the FPGA cores:

  • RXC must be connected a pin that has a I/O clock buffer, BUFIO.
  • RXD and RX_CTL must be connected to same I/O bank as RXC.
  • The Clk_Tx input clock is used for clocking out TXC. I.e. if Clk_Tx is delayed 90 deg TXC is delayed 2 ns relative TXD and TX_CTL.
  • Clk_Tx can be same as Clk, then edges of TXC, TXD and TX_CTL will be aligned.
  • Clk must be 125 MHz.

RGMII Tutorials

The following tutorials are using boards with RGMII

Ethernet On NUMATO LAB MIMAS A7 Board

Connect your FPGA