RGMII, Reduced Gigabit Media-Independent Interface, is an interface standard between a FPGA and an Ethernet PHY supporting gigabit Ethernet. RGMII is an alternative to GMII with a reduced number of signals.
RGMII is clocking data on both rising and falling clock edges, double data rate, DDR.
Default FPGA Cores support 100 and 1000 Mbps full duplex. 10 Mbps can be added to the core upon request.
|TXC||Clock signal||FPGA to PHY|
|TXD[3..0]||Data to be transmitted||FPGA to PHY|
|TX_CTL||Multiplexing of transmitter enable and transmitter error||FPGA to PHY|
|RXC||Received clock signal||PHY to FPGA|
|RXD[3..0]||Received data||PHY to FPGA|
|RX_CTL||Multiplexing of data received is valid and receiver error||PHY to FPGA|
|MDC||Management interface clock||FPGA to PHY|
|MDIO||Management interface I/O||Bidirectional|
Cores Supporting RGMII
RGMII Implementation Details
By default the FPGA cores:
- RXC must be connected a pin that has a I/O clock buffer, BUFIO.
- RXD and RX_CTL must be connected to same I/O bank as RXC.
- The Clk_Tx input clock is used for clocking out TXC. I.e. if Clk_Tx is delayed 90 deg TXC is delayed 2 ns relative TXD and TX_CTL.
- Clk_Tx can be same as Clk, then edges of TXC, TXD and TX_CTL will be aligned.
- Clk must be 125 MHz.
The following tutorials are using boards with RGMII