Transform C++ into Custom RISC-V Hardware

Instant SoC is a revolutionary design tool that compiles C++ code directly into synthesizable SystemVerilog. By automatically generating a tailored RISC-V soft CPU, optimized memories, and peripherals, it offers the fastest path from software definition to FPGA implementation.

Why choose Instant SoC?

• Software-Defined Hardware: Define peripherals like UART, SPI, I2C, and AXI4 Streams as native C++ objects.
• Instruction-Level Optimization: The generated hardware is unique to your code. Only the RISC-V instructions your application actually uses are implemented, drastically reducing logic footprint.
• Efficient Memory Scaling: Advanced static stack analysis automatically optimizes memory utilization.
• Rapid Development: Skip the complexity of manual RTL integration and move straight to functional hardware.

Example: A Simple “Hello World” The following snippet demonstrates how easily you can initialize a UART and toggle an LED using a hardware timer—all within a single C++ environment

#include "fc_io.h"
#include "fc_system.h"

int main(void)
{
//% hw_begin
    FC_IO_Clk clk(100);                 // 100 MHz
    FC_IO_Out led;  
    FC_IO_UART_TX uart_tx(115200,32);   // 32 Bytes FIFO
    FC_System_Timer timer;    
//% hw_end

    int led_state = 0x01;    

    uart_tx << "Hello World!!";

    for(;;) {
        timer.Sleep(1000, TU_ms);
        led_state = ~led_state;
        led = led_state;
    }
} 

Compilation Outputs

Upon compiling the C++ source, Instant SoC generates a complete hardware and verification package:

• SystemVerilog Source: A single, synthesizable file containing the custom-tailored RISC-V core, peripheral logic, optimized memory blocks, and the specific instruction-set subset.
• SystemVerilog Testbench: A comprehensive simulation environment for the system, including pre-configured stimuli to verify the functionality of most instantiated peripherals.
• VHDL Testbench

The generated SystemVeriog for the example above will look like:

module test(
    // FC_IO_Clk clk     100 MHz
    input logic clk,
    // FC_IO_Out led
    output logic led,
    // FC_IO_UART_TX uart_tx     32 Bytes FIFO
    output logic uart_tx
);

Versatile Integration & Multi-Core Support

The generated system is highly flexible and can be utilized as a standalone top-level module or integrated as a sub-component within a larger design hierarchy.

Because Instant SoC is engineered for extreme resource efficiency, your design is not limited to a single instance; you can easily incorporate multiple Instant SoC components within the same FPGA to handle parallel tasks or modularize complex functions.

Universal Vendor Support

Instant SoC is platform-independent. The generated code is compatible with all major FPGA vendors and toolchains, including:

• AMD / Xilinx (Vivado, ISE)
• Intel / Altera (Quartus)
• Lattice Semiconductor (Radiant, Diamond)
• Microchip / Microsemi (Libero)
• Efinix (Efinity)

Installation instructions.

Getting Started.

Instant SOC C++ Class Library