RISC-V

RISC-V is an open and free ISA (instruction set architecture) based on RISC ( reduced instruction set computer ) principles. The ISA is very suitable for implementations on FPGAs.

The project started in 2010 at the University of California, Berkeley and is today managed by the RISC-V Foundation.

There are several ISA base and extensions of RISC-V. The bases are 32, 64 and 128 bits architectures. Instant SoC is based on the 32 bits version ( RV32I) with the M (Standard Extension for Integer Multiplication and Division) extension.

The Instant SoC implementation of RISC-V is very effective and most instruction are executed within one clock cycle. The peripherals are very tight to the CPU core with minimal overhead.

The efficiency is shown with the following simple example.

#include "fc_io.h"
#include "fc_system.h"

int main()
{
//% hw_begin
    FC_IO_Clk clk(100);
    FC_IO_Out y1(8);    
    FC_IO_Out y2(8);    
//% hw_end

    int i=0;

    for(;;)
    {
        y1 = i++;
        y2 = 0x1;
        y2 = 0x00;
    }
}

This C++ code will result in the following IO signals. Note that the IOs only needs one clock cycle to be updated and the total loop is only 6 clock cycles.

RISC-V
Example output from RISC-V

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