Ethernet On Arty A7 Board

This tutorial describes how to get started with our Ethernet cores on Digilent Arty A7 development board.
The board has one Artix XC7A35 from Xilinx and a MII Ethernet interface.

Digilent Arty Ethernet

We will use the FC1002_MII core. It has Remote Programming, TCP/IP and Logic Analyzer support.

This tutorial uses Vivado Design Suite from Xilinx to build the project.


  • Xilinx Vivado installed
  • Digilent Arty board connected to USB and Ethernet

Create a new Vivado project.

  • [File]-[New Project…]
  • Select RTL Project.
  • Select xc7a35ticsg324-1L

Download Files

Add Sources to the project

  • [File]-[Add Sources…]
  • Select Add or Create Design Resources
  • Add the files ArtyTop.vhd and FC1002_MII.edn
  • [File]-[Add Sources…]
  • Select Add or Create Constraints
  • Add the file Arty_Master.xdc

Turn off DHCP Option only if necessary
The Top file is using DHCP as default. If you want to use fixed IP then:

  • Open the ArtyTop.vhd in an editor
  • Set the port signal UseDHCP to ‘0’
  • Set the port signal IP_Addr to wanted IP address in hex, e.g. xC0A8010F if

Set Bitstream settings

  • [Flow]-[Settings]-[Bitstream Settings…]
  • Check the -bin_file option

Build the project.

  • [Flow]-[Generate Bitstream]

Download bit file

  • Open Hardware Manager
  • Auto Connect
  • Select the generated bit file and program the FPGA

Program the flash with FPGA Programmer via Ethernet

  • If FPGA Programmer is not installed then download and install FPGA Programmer.
  • Start FPGA Programmer
  • Select the generated bin file and program the Arty Board. This file is typically found in ./ProjectName.runs/impl_1/.
  • Check all options (Program, Verify, Reboot)
  • Press Run to start the flash programming

From now you only need to have the board connected with Ethernet to update and program the board.

Use the logic analyzer FPGA Probe

  • If FPGA Probe is not installed then download and install FPGA Probe.
  • Start FPGA Probe
  • Select the FPGAs IP
  • Make sure Play button is active

There should now be some bit action on the screen.

You can now try to alter the top file to generate some other data in the logic analyzer.

You can now also easily use the TCP AXI4 Stream to communicate with the board via a Windows or Linux client.

Have fun!

Connect your FPGA