FC1003_MII contains functions for remote flash programming, UDP communication and a logic analyzer for debugging. All this in a single easy to use core.
The UDP interface is a standard AXI Stream interface with status signals.
Flash programming is done with FPGA Programmer.
The core is available for Xilinx 7 Series.

FC1003_MII Ethernet FPGA core

Signal Interface

Clkin1100 MHz
Resetin1Active high
UseDHCPin1'1' to use DHCP
IP_Addrin32IP address if not using DHCP
IP_Okout1DHCP ready
MII_REF_CLK_25Mout1MII continous 25 MHz reference clock
MII_RST_Nout1Phy reset, active low
MII_COLin1Collision detect
MII_CRSin1Carrier sense
MII_RX_CLKin1Receive clock
MII_CRS_DVin1Receive data valid
MII_RXDin4Receive data
MII_RXERRin1Receive error
MII_TX_CLKin1Transmit clock
MII_TXENout1Transmit enable
MII_TXDout4Transmit data
MII_MDCout1Management clock
MII_MDIOin/out1Management data
SPI/Boot Control
SPI_CSnout1Chip select
SPI_SCKout1Serial clock
SPI_MOSIout1Master out slave in
SPI_MISOin1Master in slave out
Logic Analyzer
LA0_TrigInin1Trigger input
LA0_TrigOutout1Trigger out
LA0_SampleEnin1Sample enable
UDP Basic Server
UDP0_Resetin1Reset interface, active high
UDP0_ServerPortin16UDP local server port
UDP0_Connectedout1Client connected
UDP0_OutIsEmptyout1All outgoing data acked
UDP0_TxDatain8Transmit data
UDP0_TxValidin1Transmit data valid
UDP0_TxReadyout1Transmit data ready
UDP0_TxLastin1Transmit data last
UDP0_RxDataout8Receive data
UDP0_RxValidout1Receive data valid
UDP0_RxReadyin1Receive data ready
UDP0_RxLastout1Transmit data last


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This HDL code and netlists are only free to use for non - commercial users and for evaluation purpose. Commercial use needs a commercial license.
The HDL code and netlists are distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

VHDL Component: FC1003_MII.vhd
Verilog Module: FC1003_MII.vh
Xilinx 7 Series Netlist: FC1003_MII.edn
Xilinx Spartan 6 Netlist: FC1003_MII.ngc

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