Instant SoC Class Library  1.2
FC_Wishbone Class Reference

Wishbone bus master
This class makes it very easy to connect Wishbone slaves to Instant SoC generated systems.
It is possible to let Instant SoC embed and map your Wishbone slave directly by using a constructor with a source file argument.
See Wishbone Instant SoC for details.
Any number of Wishbone instances are allowed.
. More...

Inheritance diagram for FC_Wishbone:

Public Member Functions

 FC_Wishbone (const char *file_name)
 
 FC_Wishbone (int address_width, int data_width_out, int data_width_in)
 
 FC_Wishbone (const char *file_name, int address_width, int data_width_out, int data_width_in)
 
void Reset ()
 
void Write (U32 v, U32 addr)
 
void Write (U32 v)
 
void Write (const U32 *pD, U32 nData, U32 addr)
 
void WriteNoWait (U32 v, U32 addr)
 
void WriteNoWait (U32 v)
 
void WriteNoWait (const U32 *pD, U32 nData, U32 addr)
 
U32 Read ()
 
U32 Read (U32 addr)
 
void Read (U32 addr, U32 *pD, U32 nData)
 

Detailed Description

Wishbone bus master
This class makes it very easy to connect Wishbone slaves to Instant SoC generated systems.
It is possible to let Instant SoC embed and map your Wishbone slave directly by using a constructor with a source file argument.
See Wishbone Instant SoC for details.
Any number of Wishbone instances are allowed.
.

Constructor & Destructor Documentation

◆ FC_Wishbone() [1/3]

FC_Wishbone::FC_Wishbone ( const char *  file_name)
inline

Constructor
Instant SoC parses the source file. Verilog and VHDL Wishbone slaves are supported.
Wishbone signals are automatically mapped to the internal system.
Non Wishbone signals are mapped to the generated system port.

Parameters
file_nameA string representing the name of the file to open. Verilog (*.verilog) and VHDL (*.vhd) files are supported.

◆ FC_Wishbone() [2/3]

FC_Wishbone::FC_Wishbone ( int  address_width,
int  data_width_out,
int  data_width_in 
)
inline

Constructor
Use this constructor to expose the Wishbone bus signal out of the generated SoC.
This constructor adds the following signals to the interface:
<name>_RST_O : out std_logic
<name>_ADR_O : out std_logic_vector(address_width-1 downto 0) when (address_width > 0)
<name>_DAT_I : in std_logic_vector(data_width-1 downto 0) when (data_width_in > 0)
<name>_DAT_O : out std_logic_vector(data_width-1 downto 0) when (data_width_out > 0)
<name>_WE_O : out std_logic when (data_width_out > 0)
<name>_STB_O : out std_logic
<name>_ACK_I : in std_logic
<name>_CYC_O : out std_logic
where <name> is the c++ object name.
Any number of instances are allowed.

Parameters
address_widthWidth of the address vector. 0 to 32.
data_width_outWidth of the master data out. 0 to 32.
data_width_inWidthe of the master data in vector. 0 to 32.

◆ FC_Wishbone() [3/3]

FC_Wishbone::FC_Wishbone ( const char *  file_name,
int  address_width,
int  data_width_out,
int  data_width_in 
)
inline

Constructor
If file does not exist Instant SoC creates a template that is a good starting point to write a Wishbone slave.

Parameters
file_nameA string representing the name of the file to open or create. Verilog (*.verilog) and VHDL (*.vhd) files are supported.
address_widthWidth of the address vector. 0 to 32.
data_width_outWidth of the master data out. 0 to 32.
data_width_inWidthe of the master data in vector. 0 to 32.

Member Function Documentation

◆ Read() [1/3]

U32 FC_Wishbone::Read ( )
inline

Read

Performs a read cycle at last read address + 1

◆ Read() [2/3]

U32 FC_Wishbone::Read ( U32  addr)
inline

Read

Performs a read cycle from Wishbone slave.

Parameters
addrRead address seen in Wishbone slave

◆ Read() [3/3]

void FC_Wishbone::Read ( U32  addr,
U32 *  pD,
U32  nData 
)
inline

Read

Reads a number of words to RAM from Wishbone slave.

Parameters
addrRead address seen in Wishbone slave
pDPointer to destination
nDataNumber of data to be read

◆ Reset()

void FC_Wishbone::Reset ( )
inline

Reset

Performs a pulse on <name>_RST_O, RST_I at slave

◆ Write() [1/3]

void FC_Wishbone::Write ( const U32 *  pD,
U32  nData,
U32  addr 
)
inline

Write

Writes a vector from RAM to Wishbone slave

Parameters
pDPointer to data to be written
nDataNumber of data to be written
addrDestination address seen in Wishbone slave

◆ Write() [2/3]

void FC_Wishbone::Write ( U32  v)
inline

Write

Performs a write cycle on the Wishbone bus at last write address + 1. This speeds up consequtive writes.

Parameters
vValue to write

◆ Write() [3/3]

void FC_Wishbone::Write ( U32  v,
U32  addr 
)
inline

Write

Performs a write cycle on the Wishbone bus

Parameters
vValue to write
addrDestination address seen in Wishbone slave

◆ WriteNoWait() [1/3]

void FC_Wishbone::WriteNoWait ( const U32 *  pD,
U32  nData,
U32  addr 
)
inline

WriteNoWait

Writes a vector from RAM to Wishbone slave without waiting for ACKs.

Parameters
pDPointer to data to be written
nDataNumber of data to be written
addrDestination address seen in Wishbone slave

◆ WriteNoWait() [2/3]

void FC_Wishbone::WriteNoWait ( U32  v)
inline

WriteNoWait

Performs a write cycle without waiting for ACK at last write address + 1. This speeds up consequtive writes.

Parameters
vValue to write

◆ WriteNoWait() [3/3]

void FC_Wishbone::WriteNoWait ( U32  v,
U32  addr 
)
inline

WriteNoWait

Performs a write cycle without waiting for ACK

Parameters
vValue to write
addrDestination address seen in Wishbone slave