Instant SoC Getting Started

This tutorial will show how to get started with Instant SoC. It is assumed that the user is familiar with Vivado or similar VHDL simulator.

Start Instant SoC application that is found in the Windows start menu.

Select or create a folder where you want to have your project.

Select the gcc root directory. This folder should contain (bin, include etc)

Instant SOC Risc-V Setup

Select “Create Example”.

Press “Setup Project Folder” to generate necessary files.

Now start Visual Studio Code. Open the folder you created, [File] – [Open Folder…]

Click on the “example.cpp” file to open it.

The “example-cpp” file looks like:

#include "fc_io.h"
#include "fc_system.h"

int main()
{
    //% hw_begin
    FC_IO_Clk clk(100);
    FC_IO_Out counter(8);
    FC_System_Timer timer;
    //% hw_end
    int counter_value = 0;
    timer.Start(1, TU_us);
    for (;;)
    {
        timer.WaitTimer();
        counter = counter_value++;
    }
}

The hardware (peripherals) are defined between //% hw_begin and //%hw_end. The first hardware component must be a clock. In this case the system clock (clk) is 100 MHz.

Bulid the system by pressing Ctrl+Shift+B.

You can now see that “example.vhd”, “example_TB.vhd” and “example.vh” files are created in your folder.

Now we will add an UART that sends a “Hello World” message. Place the cursor in the “hw” section.

When you type “FC_IO” a drop-list with all IO classes is shown.

Add an FC_IO_UART_TX object with the baudrate as constructor argument.

Add a stream “hello world” message. The code should now look like:

#include "fc_io.h"
#include "fc_system.h"

int main()
{
    //% hw_begin
    FC_IO_Clk clk(100);
    FC_IO_Out counter(8);
    FC_IO_UART_TX tx(115200);
    FC_System_Timer timer;
    //% hw_end
    int counter_value = 0;

    tx << "Hello World!";
    
    timer.Start(1, TU_us);
    for (;;)
    {
        timer.WaitTimer();
        counter = counter_value++;
    }
}

Build the system (Ctrl+Shift+B). This results in the following entity:

--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity example is
    port(
        clk : in std_logic;
        counter : out std_logic_vector(7 downto 0);
        tx : out std_logic
    );
end entity;

architecture IMPL of example is
...

Open Vivado (or other vhdl simulator) and create a new project. Add these two vhdl files to the project (simulation). Select tutorial_TB as top-level and run the simulation.

The “example.vhd” can be used as a top level or lower level component.

Connect your FPGA