Instant SoC (System on Chip) is a new innovative system that compiles C++ code directly to synthesize-able VHDL. The VHDL code includes a RISC-V soft CPU, CPU instructions, memories and peripherals. This is the fastest and easiest way to create a CPU system for FPGAs.
The CPU peripherals like logic IOs, UARTs, SPI, I2C, AXI4 Streams etc are defined as C++ objects.
The VHDL code is optimized with respect to the generated RISC-V instructions. Only used instructions are implemented. The memories are optimized using static stack analysis.
The following example shows a very simple “Hello World” application that sends a message on an UART and then toggles a LED every second using a timer.
#include "fc_io.h"
#include "fc_system.h"
int main(void)
{
//% hw_begin
FC_IO_Clk clk(100); // 100 MHz
FC_IO_Out led;
FC_IO_UART_TX uart_tx(115200,32); // 32 Bytes FIFO
FC_System_Timer timer;
//% hw_end
int led_state = 0x01;
uart_tx << "Hello World!!";
for(;;) {
timer.Sleep(1000, TU_ms);
led_state = ~led_state;
led = led_state;
}
}
When compiling the C++ code the following outputs are generated:
- A VHDL file containing all RISC-V, peripherals, memories and instructions.
- VHDL Testbench using the system, including stimuli for most of the peripherals.
- Verilog header file.
The generated VHDL entity for the example above will look like:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hello_world is
port(
clk : in std_logic; -- 100 MHz
led : out std_logic;
uart_tx : out std_logic -- 32 Bytes FIFO
);
end entity;
The generated system can be used as a top-level or as a lower level component. Since the code is very optimized your system can contain several Instant SoC components.
All major FPGA providers (Xilinx, Intel/Altera, Lattice) are supported.