FC1004_RGMII

Description


FC1004_RGMII supports RGMII gigabit Ethernet PHY interface. The core contains functions for remote SPI boot flash programming, UDP communication, TCP communication and a logic analyzer for remote debugging. All this in a single easy to use core.
The UDP and TCP interfaces are standard AXI4 Streams with status/setup signals.
SPI boot flash programming is done with FPGA Programmer.
The core is available for Xilinx 7 Series (Spartan, Artix, Kintex, Virtex, Zynq).

FC1004_RGMII Ethernet FPGA core

Signal Interface

NameDirectionWidthRemarks
Sys/Common
Clkin1125 MHz
Clk_Txin1125 MHz RGMII Transmit clock
Resetin1Active high
UseDHCPin1'1' to use DHCP
IP_Addrin32IP address if not using DHCP
IP_Okout1DHCP ready
TCP Basic Server
TCP0_Servicein16Service
TCP0_ServerPortin16TCP local server port
TCP0_Connectedout1Client connected
TCP0_AllAckedout1All outgoing data acked
TCP0_nTxFreeout16Number of free bytes in outgoing buffer
TCP0_nRxDataout16Number of bytes in receiving buffer
TCP0_TxDatain8Transmit data
TCP0_TxValidin1Transmit data valid
TCP0_TxReadyout1Transmit data ready
TCP0_RxDataout8Receive data
TCP0_RxValidout1Receive data valid
TCP0_RxReadyin1Receive data ready
MAC/RGMII
RGMII_TXCout1
RGMII_TXDout4
RGMII_TX_CTLout1
RGMII_RXCin1
RGMII_RXDin4
RGMII_RX_CTLin1
RGMII_MDCout1
RGMII_MDIOin/out1
SPI/Boot Control
SPI_CSnout1Chip select
SPI_SCKout1Serial clock
SPI_MOSIout1Master out slave in
SPI_MISOin1Master in slave out
Logic Analyzer
LA0_TrigInin1Trigger input
LA0_Clkin1Clock
LA0_TrigOutout1Trigger out
LA0_Signalsin32Signals
LA0_SampleEnin1Sample enable
UDP Basic Server
UDP0_Resetin1Reset interface, active high
UDP0_Servicein16Service
UDP0_ServerPortin16UDP local server port
UDP0_Connectedout1Client connected
UDP0_OutIsEmptyout1All outgoing data acked
UDP0_TxDatain8Transmit data
UDP0_TxValidin1Transmit data valid
UDP0_TxReadyout1Transmit data ready
UDP0_TxLastin1Transmit data last
UDP0_RxDataout8Receive data
UDP0_RxValidout1Receive data valid
UDP0_RxReadyin1Receive data ready
UDP0_RxLastout1Transmit data last

Downloads

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This HDL code and netlists are only free to use for non - commercial users and for evaluation purpose. Commercial use needs a commercial license.
The HDL code and netlists are distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

VHDL Component: FC1004_RGMII.vhd
Verilog Module: FC1004_RGMII.vh
Xilinx 7 Series Netlist: FC1004_RGMII.edn

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